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    Computer Architecture
    COMP3147
    Progress0 / 24 topics
    Topics
    1. Digital Hardware Design: Transistors and Digital logic2. Hardware description languages (Verilog)3. Instruction Set Architecture: Instruction types and mixes4. Addressing modes5. RISC vs. CISC architectures6. Exceptions in instruction sets7. Scalar Pipelines: Data dependencies8. Static scheduling9. Pipeline performance analysis10. VLIW Pipelines: Local scheduling11. Loop unrolling and Software pipelining12. Trace scheduling13. Deferred exceptions and Predicated execution14. IA64 architecture15. Dynamic Pipelines: Dynamical scheduling16. Register renaming17. Speculative execution18. Trace cache19. Thread-Level Parallelism: Cache coherency20. Sequential consistency21. Multithreading22. Symmetric multiprocessing23. Transactional memory24. Data-Level Parallelism: GPU programming
    COMP3147›Transactional memory
    Computer ArchitectureTopic 23 of 24

    Transactional memory

    3 minread
    490words
    Beginnerlevel

    ⭐ Transactional Memory (TM)

    1. Definition

    Transactional Memory (TM) is a concurrency control mechanism that allows multiple threads to execute memory operations in atomic blocks called transactions, simplifying synchronization in parallel programming.

    A transaction is a sequence of read/write operations on shared memory that either commits completely (all operations succeed) or aborts entirely (none of the operations take effect), ensuring atomicity.


    2. Purpose

    1. Simplify parallel programming: Avoid explicit locks or semaphores.
    2. Reduce deadlocks and race conditions: Transactions automatically handle conflicts.
    3. Increase parallelism: Multiple threads can speculatively execute transactions concurrently.

    3. Key Concepts

    a) Atomicity

    • A transaction appears as a single, indivisible operation.
    • Either all memory updates occur or none occur.

    b) Isolation

    • Changes made by a transaction are not visible to other threads until the transaction commits.

    c) Consistency

    • Memory remains in a valid state before and after a transaction.

    d) Conflict Detection

    • Hardware or software tracks read/write sets of transactions.
    • Conflicts occur if two transactions access the same memory location with at least one write.

    e) Commit or Abort

    • Commit: Transaction completes successfully; updates are made visible.
    • Abort: Transaction fails due to conflicts; memory is restored to its previous state.

    4. Types of Transactional Memory

    A) Hardware Transactional Memory (HTM)

    • Transaction management is handled by CPU hardware.
    • Very fast, minimal software overhead.
    • Example: Intel TSX (Transactional Synchronization Extensions).

    B) Software Transactional Memory (STM)

    • Transactions are managed by software libraries or runtime.
    • Slower than HTM but more flexible and portable.

    C) Hybrid Transactional Memory (HyTM)

    • Combines hardware and software approaches for better performance and flexibility.

    5. Example Scenario

    Suppose two threads T1 and T2 access a shared variable X:

    Without TM (lock-based):

    lock(L)
    X = X + 1
    unlock(L)
    

    With TM:

    transaction {
        X = X + 1
    }
    
    • If T1 and T2 conflict (both modify X at the same time), one transaction aborts and retries.
    • No explicit locks are needed.

    6. Advantages of Transactional Memory

    1. Simplifies parallel programming by avoiding explicit locks.
    2. Reduces deadlocks and priority inversion.
    3. Allows higher concurrency than coarse-grained locks.
    4. Optimistic execution: Threads execute in parallel assuming conflicts are rare.

    7. Limitations

    1. Conflict overhead: Aborted transactions waste computation.
    2. Limited hardware resources in HTM (e.g., cache size limits).
    3. Not suitable for I/O operations inside transactions.
    4. Complexity in nested transactions and long-running transactions.

    8. Relation to Other Concepts

    Concept Relation to TM
    Locks / Mutexes TM is a lock-free alternative for synchronization.
    Multithreading / TLP TM enables safe concurrent access to shared memory by multiple threads.
    Speculative Execution TM relies on speculatively executing transactions, rolling back if conflicts occur.
    Cache Coherency Necessary to detect conflicts between transactions in hardware TM.

    9. Exam-Friendly Summary

    • Transactional Memory: Allows concurrent threads to execute memory operations atomically without explicit locks.
    • Key Features: Atomicity, Isolation, Consistency.
    • Types: Hardware TM (HTM), Software TM (STM), Hybrid TM (HyTM).
    • Advantages: Simplifies synchronization, reduces deadlocks, increases concurrency.
    • Limitations: Abort overhead, hardware limits, not ideal for I/O-heavy operations.
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    Data-Level Parallelism: GPU programming

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